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1 nv/hz low noise 210c instrumentation amplifier data sheet ad8229 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011C2012 analog devices, inc. all rights reserved. features designed and guaranteed for 210c operation low noise 1 nv/hz input noise 45 nv/hz output noise high cmrr 126 db cmrr (minimum), g = 100 80 db cmrr (minimum) to 5 khz, g = 1 excellent ac specifications 15 mhz bandwidth (g = 1) 1.2 mhz bandwidth (g = 100) 22 v/s slew rate thd: ?130 dbc (1 khz, g = 1) versatile 4 v to 17 v dual supply gain set with single resistor (g = 1 to 1000) specified temperature range ?40c to +210c, sbdip package ?40c to +175c, soic package applications down-hole instrumentation harsh environment data acquisition exhaust gas measurements vibration analysis functional block diagram top view (not to scale) ?in 1 r g 2 r g 3 +in 4 +v s 8 v out 7 ref 6 ?v s 5 ad8229 09412-001 figure 1. 100 80 60 40 20 0 ?20 ?40 ?60 ?80 ?100 v osi ( v) ?55 ?35 ?15 5 25 45 65 85 105 125 145 165 185 205 225 temperature (c) 09412-016 figure 2. typical input offset vs. temperature (g = 100) general description the ad8229 is an ultralow noise instrumentation amplifier designed for measuring small signals in the presence of large common-mode voltages and high temperatures. the ad8229 has been designed for high temperature operation. the process is dielectrically isolated to avoid leakage currents at high temperatures. the design architecture was chosen to compensate for the low v be voltages at high temperatures. the ad8229 excels at measuring tiny signals. it delivers industry leading 1 nv/hz input noise performance. the high cmrr of the ad8229 prevents unwanted signals from corrupting the acquisition. the cmrr increases as the gain increases, offering high rejection when it is most needed. the ad8229 is one of the fastest instrumentation amplifiers available. its current feedback architecture provides high bandwidth at high gain, for example, 1.2 mhz at g = 100. the design includes circuitry to improve settling time after large input voltage transients. the ad8229 was designed for excellent distortion performance, allowing use in demanding applications such as vibration analysis. gain is set from 1 to 1000 with a single resistor. a reference pin allows the user to offset the output voltage. this feature can be useful when interfacing with analog-to-digital converters. for the most demanding applications, the ad8229 is available in an 8-lead side-brazed ceramic dual in-line package (sbdip). for space-constrained applications, the ad8229 is available in an 8-lead plastic standard small outline package (soic).
ad8229 data sheet rev. b | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block di agram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 6 predicted lifetime vs. operating temperature ........................ 6 thermal resistance ...................................................................... 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 theory of operation ...................................................................... 17 architecture ................................................................................ 17 gain selection ............................................................................. 17 reference terminal .................................................................... 17 input voltage range ................................................................... 18 layout .......................................................................................... 18 input bias current return path ............................................... 19 input protection ......................................................................... 19 radio frequency interference (rfi) ........................................ 19 calculating the noise of the input stage ................................. 20 outli ne dimensions ....................................................................... 21 ordering guide .......................................................................... 21 revision history 2 /1 2 rev. a to rev. b added 8 - lead soic ........................................................... universal changes to features section and general description sec tion ...... 1 change s to table 1 ............................................................................ 3 changes to table 2, thermal resistance section, and table 3 ... 6 updated outline dimensions ....................................................... 21 changes to ordering guide .......................................................... 21 9 /11 rev. 0 to rev. a c hanges to features section and general description section ...... 1 changes to table 2 ............................................................................ 6 a d ded predicted lifetime vs. operating temperature section and figure 3 ; renumbered sequentially .............................................. 6 changes to figure 18 and figure 1 9 ............................................. 10 changes to figure 2 4 to figure 2 8 ................................................ 11 changes to figure 29 and figure 30 ............................................. 12 changes to figure 48 ...................................................................... 15 changes to figure 5 6 ...................................................................... 17 changes to power supplies section .............................................. 18 1/1 1 revision 0: initial version
data sheet ad8229 rev. b | page 3 of 24 specifications +v s = 15 v, ?v s = ?15 v, v ref = 0 v, t a = 25c, g = 1, r l = 10 k, unless otherwise noted. table 1 . parameter test conditions/comments min typ max unit common - mode rejection ratio (cmrr) cmrr dc to 60 hz with 1 k source imbala nce v cm = 10 v g = 1 86 db temperature drift t a = ?40c to +210c 300 nv/v/ c g = 10 106 db temperature drift t a = ?40c to +210c 30 nv/v/ c g = 100 126 db temperature drift t a = ?40c to +210c 3 nv/v/ c g = 1000 t a = ?40c to +210c 134 db cmrr at 5 khz v cm = 10 v g = 1 80 db g = 10 90 db g = 100 90 db g = 1000 90 db voltage noise v in +, v in ? = 0 v spectral density 1 : 1 khz input voltage noise, e ni 1 1.1 nv/hz output voltage noise, e no 45 50 nv/hz peak to peak: 0.1 hz to 10 hz g = 1 2 v p -p g = 1000 100 nv p - p current noise spectral density: 1 khz 1.5 pa/hz peak to peak: 0.1 hz to 10 hz 100 pa p -p voltage offset v os = v osi + v oso /g input offset, v osi 100 v average tc t a = ?40c to +210c 0.1 1 v/c output offset, v oso 1000 v average tc t a = ?40c to +210c 3 10 v/c offset rti vs. supply (psr) v s = 5 v to 15 v g = 1 t a = ?40c to +210c 86 db g = 10 t a = ?40c to +210c 106 d b g = 100 t a = ?40c to +210c 126 db g = 1000 t a = ?40c to +210c 130 db input current input bias current 70 na high temperature t a = 210c 200 na input offset current 35 na high temperature t a = 210c 50 na
ad8229 data sheet rev. b | page 4 of 24 parameter test conditions/comments min typ max unit dynamic response small signal bandwidth C3 db g = 1 15 mhz g = 10 4 mhz g = 100 1.2 mhz g = 1000 0.15 mhz settling time 0.01% 10 v step g = 1 0.75 s g = 10 0.65 s g = 100 0.85 s g = 1000 5 s settling time 0.001% 10 v step g = 1 0.9 s g = 10 0.9 s g = 100 1.2 s g = 1000 7 s slew rate g = 1 to 100 22 v/s thd ( first five harmonics) f = 1 khz, r l = 2 k, v out = 10 v p - p g = 1 C 130 dbc g = 10 C 116 dbc g = 100 C 113 dbc g = 1000 C 111 dbc thd + noise f = 1 khz, r l = 2 k, v out = 10 v p - p, g = 100 0.0005 % gain 2 g = 1 + (6 k /r g ) gain range 1 1000 v/v gain error v out = 10 v g = 1 0.01 0.03 % g = 10 0.05 0.3 % g = 100 0.05 0.3 % g = 1000 0.1 0.3 % gain nonlinearity v out = ?10 v to +10 v g = 1 to 1000 r l = 10 k 2 ppm gain vs. temperature g = 1 t a = ?40c to +210c 2 5 ppm/c g > 10 t a = ?40c to +210c ?100 ppm/c input impedance (pin to ground) 3 1.5||3 g ||p f input operating voltage range 4 v s = 5 v to 18 v for dual supplies ?v s + 2.8 +v s ? 2.5 v over temperature t a = ?40c to +210c ?v s + 2.8 +v s ? 2.5 v output output swing , r l = 2 k ?v s + 1.9 +v s ? 1.5 v high temperature, sbdip package t a = 210c ?v s + 1.1 +v s ? 1.1 v high temperature, soic package t a = 175c ?v s + 1.2 +v s ? 1.1 v output swing , r l = 10 k ?v s + 1.8 +v s ? 1.2 v high temperature, sbdip packag e t a = 210c ?v s + 1.1 +v s ? 1.1 v high temperature, soic package t a = 175c ?v s + 1.2 +v s ? 1.1 v short - circuit current 35 ma
data sheet ad8229 rev. b | page 5 of 24 parameter test conditions/comments min typ max unit reference input r in 10 k i in v in +, v in ? = 0 v 70 a voltage range ?v s +v s v reference gain to output 1 v/v reference gain error 0.01 % power supply operating range 4 17 v quiescent current 6.7 7 ma high temperature, sbdip package t a = 210c 12 ma high temperature, soic package t a = 175c 11 ma temperature range for specified performance 5 sbdip package ?40 +210 c soic package ? 40 +175 c 1 total voltage nois e = (e ni 2 + (e no /g) 2 )+ e rg 2 ). see the theory of operation section for more information. 2 these specifications do not include the tolerance of the external gain setting resistor, r g . for g>1, r g errors should be a dded to the specifications given in this table. 3 differential and common - mode input impedance can be calculated from the pin impedance: z diff = 2(z pin ); z cm = z pin /2. 4 input voltage range of the ad8229 input stage only. the input range can depend on the common - mode voltage, differential voltage, gain, and reference voltage. see the input voltage range section for more details. 5 for the guaranteed operation time at the maximum specified temperature, refer to the predicted lifetime vs. operating temperature section.
ad8229 data sheet rev. b | page 6 of 24 absolute maximum rat ings table 2. parameter rating supply voltage 17 v output short - circuit current duration indefinite max imum voltage at C in, +in 1 v s differential input voltage 1 gain 4 v s 4 > gain > 50 50 v/g ain gain 50 1 v maximum voltage at ref v s storage temperature range ? 65c to +150c specified temperature range sbdip ? 40c to +210c soic ?40c to +175c maximum junction temperature sbdip 245c soic 200c esd human body model 4 kv charge device model 1.5 kv machine model 200 v 1 for voltages beyond these limits , use input protection resistors. see the theory of operation section for more information. stress es above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specif ication is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. predicted lifetime v s. operating temperature comprehensive reliability testing is performed on the ad8229 . product lifetimes at extended operating temperature are obtained using high temperature operating life (htol ). lifetimes are predicted from the arrhenius equation, taking into account potential design and manufacturing failure mechanis m assump - tions. htol is p erformed to jedec jesd22 - a108. a minimum of three wafer fab and assembly lots are processed through htol at the maximum operating temperature. comprehensive reliability testing is performed on all analog devices, inc., high tempera ture (ht) products. 1 100k 10k 1k 100 10 120 210200190180170160150140130 predicted lifetime (hours) operating temperature (c) 09412-200 figure 3 . predicted lifetime vs. operating temperature r ef er to the ad8229 predicted lifetime vs. operating temperature document for the most up - to - date reliability data . thermal resistance ja is spe cified for a device in free air using a 4 - layer jedec printed circuit board (pcb). table 3 . package type ja unit 8- lead sb dip 100 c/w 8- lead soic 121 c/w esd caution
data sheet ad8229 rev. b | page 7 of 24 pin configuration and function descripti ons top view (not to scale) ?in 1 r g 2 r g 3 +in 4 +v s 8 v out 7 ref 6 ?v s 5 ad8229 09412-003 figure 4 . pin configuration table 4 . pin function descriptions pin no. mnemonic description 1 ?in negative input terminal . 2, 3 r g g ain setting termina ls. place resistor across the r g pins to set the gain. g = 1 + (6 k /r g ). 4 +in positive input terminal. 5 ?v s negative power supply terminal . 6 ref reference voltage terminal. drive this terminal with a low impedance voltage source to level - shift the o utput . 7 v out output terminal . 8 +v s positive power supply terminal .
ad8229 data sheet rev. b | page 8 of 24 typical performance characteristics t = 25c, v s = 15, v ref = 0, r l = 2 k?, unless otherwise noted. 60 50 40 30 20 10 0 ?60 ?40 ?20 20 0 v osi 15v ( v) hits 40 60 n: 200 mean: 12.2 : 8.2 09412-004 figure 5 . typical distribution of input offset voltage v oso 15v ( v) hits 35 30 20 25 15 5 10 0 800 ?600 ?400 ?200 0 200 400 600 n: 200 mean: 0.9 : 161.2 09412-005 figure 6 . typical distribution of output offset voltage 40 35 30 20 25 15 5 10 0 ?50 ?40 ?20 ?10 ?30 10 0 i bias ( na ) hits 20 30 inverting noninverting n: 200 mean: ?6.1 : 6.7 n: 200 mean: ?10.1 : 6.9 09412-006 figure 7 . typical distribution of input bias current i bias offset ( na ) hits n: 201 mean: 4.0 : 0.7 60 50 30 40 20 10 0 0 2 4 6 8 09412-007 figure 8 . typical distribution of input offset curren t hits ?40 ?60 ?20 0 20 40 60 20 0 40 60 80 100 120 cmrr g1 ( v/v) n: 200 mean: 10.9 : 3.7 09412-008 figure 9 . typical distribution of common mode rejection, g = 1 hits 09412-015 ?60 ?40 ?20 0 20 0 5 10 15 20 25 30 35 n inv g error g1 10k 15v ( v/v) n: 198 mean: ?9.1 : 9.9 figure 10 . typical distribution of gain error, g = 1
data sheet ad8229 rev. b | page 9 of 24 ?3 ?2 ?1 0 1 2 3 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 common-mode vo lt age (v) output vo lt age (v) g = 1, v s = 5v 25c 210c 09412-009 figure 11 . input common - mode voltage vs. output voltage, dual supply, v s = 5 v; g = 1 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 12 output vo lt age (v) common-mode vo lt age (v) g = 1, v s = 12v 25c 210c 09412-010 figure 12 . input common - mode voltage vs. output voltage, dual supply , v s = 12 v; g = 1 ?14 ?10 ?6 ?12 ?8 ?4 ?2 0 2 4 6 10 8 12 14 ?15 ?10 ?5 0 5 10 15 output vo lt age (v) common-mode vo lt age (v) g = 1, v s = 15v 25c 210c 09412-0 11 figure 13 . input common - mode voltage vs. output voltage, dual supply , v s = 15 v; g = 1 ?3 ?2 ?1 0 1 2 3 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 common-mode vo lt age (v) output vo lt age (v) g = 100, v s = 5v 25c 210c 09412-012 figure 14 . input common - mode voltage vs. output voltage, dual supply, v s = 5 v; g = 100 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 12 output vo lt age (v) common-mode vo lt age (v) g = 100, v s = 12v 25c 210c 09412-013 figure 15 . input common - mode voltage vs. output voltage, dual supply , v s = 12 v; g = 1 00 ?14 ?10 ?6 ?12 ?8 ?4 ?2 0 2 4 6 10 8 12 14 ?15 ?10 ?5 0 5 10 15 output vo lt age (v) common-mode vo lt age (v) g = 100, v s = 15v 25c 210c 09412-014 figure 16 . input common - mode voltage vs. output voltage, dual supply , v s = 15 v; g = 100
ad8229 data sheet rev. b | page 10 of 24 ?12.28v 12.60v ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 12 14 input bias current (na) common-mode vo lt age (v) 09412-068 figure 17 . input bias current vs. common - mode voltage frequency (hz) 0 20 40 60 80 100 120 140 160 1 10 10 0 1k 10k 100 k 1m 09412 - 069 positive psrr (db) gain = 1 gain = 1000 gain = 10 gain = 100 figure 18 . positive psrr vs. frequency frequency (hz) 0 20 40 60 80 100 120 140 negative psr r (db) 160 1 10 10 0 1k 10k 100 k 1m 09412 - 070 gain = 1 gain = 1000 gain = 10 gain = 100 figure 19 . negative psrr vs. frequency ?30 ?20 ?10 0 10 20 30 40 50 60 70 100 1k 10k 100k 1m 10m 100m gain (db) frequenc y (hz) gain = 1 gain = 1000 gain = 100 gain = 10 v s = 15v 09412-017 figure 20 . gain vs. frequency 0 20 40 60 80 100 120 140 160 1 10 100 1k 10k 100k 1m cmrr (db) frequenc y (hz) gain = 1 gain = 1000 gain = 10 gain = 100 bandwidth limited 09412-018 figure 21 . cmrr vs. frequency 0 20 40 60 80 100 120 140 160 1 10 100 1k 10k 100k 1m cmrr (db) frequenc y (hz) gain = 1 gain = 1000 gain = 10 gain = 100 bandwidth limited 09412-019 figure 22 . cmrr vs . frequency, 1 k source imbalance
data sheet ad8229 rev. b | page 11 of 24 0 2 4 6 8 10 12 0 100 200 300 400 500 600 700 change in input offset vo lt age ( v) w arm-u p time (s) 09412-071 figure 23 . change in input offset voltage (v osi ) vs. warm - up time ?10.0 ? 7.5 ? 5.0 ? 2.5 0 2.5 5.0 7.5 1 0.0 ?200 ?150 ?100 ?50 0 50 100 150 200 ? input o ffset curr ent (na) input bias curr e nt (na) temperat ur e (c) 09412 - 072 55 ?25 5 35 65 95 125 155 185 215 curr ent in put o ff set curr ent input bias figure 24 . input bias current and input offset current vs. temperature ?250 ?200 ?150 ?100 ?50 0 50 100 150 gain e rr or (v/v) 09412 - 073 ?55 ?25 5 35 65 95 125 155 185 215 temperat ur e (c) figure 25 . gain error vs. temperature, g = 1, normalized at 25 c ?10 ?5 0 5 10 15 20 ?55 ?2 5 5 35 65 95 125 155 185 215 cm rr (v/v) temperat ur e (c) 09412 - 023 figure 26 . cmr r vs. temperature, g = 1, normalized at 25 c 0 2 4 6 8 10 12 ?55 ?2 5 5 35 65 95 125 155 185 215 supply curr ent (ma) temperat ur e (c) 09412 - 074 figure 27 . supply current vs. temperature, g = 1 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 short ci rcu it curr ent (ma) i short? i short+ ?55 ?25 5 35 65 95 125 155 185 215 temperat ur e (c) 09412 - 075 figure 28 . short - circuit current vs. temperature, g = 1
ad8229 data sheet rev. b | page 12 of 24 +sr ?sr 0 5 10 15 20 25 30 slew rate (v / s) ?55 ?25 5 35 65 95 125 155 185 215 temperat ur e (c) 09412 - 076 figure 29 . slew rate vs. temperature, v s = 15 v, g = 1 +sr ?sr 0 5 10 15 20 25 slew rate (v / s) ?55 ?25 5 35 65 95 125 155 185 215 tempe ra t ur e (c) 09412 - 077 figure 30 . slew rate vs. temperature, v s = 5 v, g = 1 4 6 8 10 12 14 16 18 input vo lt age (v) referred t o supp ly vo lt ages supply vo lt age (v s ) ?55c ?40c +25c +85c +125c +150c +210c +225c +v s ?v s ?1.0 ?2.0 +1.0 +2.0 +2.5 ?0.5 ?1.5 ?2.5 +1.5 +1.5 09412-028 figure 31 . input voltage limit vs. supply voltage 4 6 8 10 12 14 16 18 output vo lt age swing (v) referred t o supp ly vo lt ages supply vo lt age (v s ) ?55c ?40c +25c +85c +125c +150c +210c +225c +v s ?v s ?0.8 +0.8 +1.6 +2.0 ?0.4 ?1.2 +1.2 +0.4 09412-029 figure 32 . output voltage swing vs. supply voltage, r l = 10 k 4 6 8 10 12 14 16 18 output vo lt age swing (v) referred t o supp ly vo lt ag es supply vo lt age (v s ) ?55c ?40c +25c +85c +125c +150c +210c +225c +v s ?v s ?0.8 +0.8 +1.6 +2.0 ?0.4 ?1.2 +1.2 +0.4 09412-030 figure 33 . output voltage swing vs. supply voltage, r l = 2 k ?15 ?10 ?5 0 5 10 15 100 1k 10k 100k output vo lt age swing (v) load () ?55c ?40c +25c +85c +125c +150c +210c +225c v s = 15v 09412-031 figure 34 . output voltage swing vs. load resistance
data sheet ad8229 rev. b | page 13 of 24 10 100 1m 5m output voltage swing (v) referred to supply voltages output current (a) +v s ?v s +0.4 ?0.4 ?0.8 ?1.2 +0.8 +1.2 +1.6 ?1.6 v s = 15v +1.8 ?55c ?40c +25c +85c +125c +150c +210c +225c 09412-032 figure 35 . output voltage swing vs. output current ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 nonlinearit y (ppm/div) output vo lt age (v) gain = 1 09412-083 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 figure 36 . gain nonlinearity, g = 1, r l = 10 k ?10 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 nonlinearit y (ppm/div) output vo lt age (v) gain = 1000 09412-084 figure 37 . gain nonlinearity, g = 1 00 0, r l = 10 k 0.1 1 10 100 1000 1 10 100 1k 10k 100k noise (nv/hz) frequenc y (hz) gain = 1 gain = 1000 gain = 10 gain = 100 09412-037 figure 38 . voltage noise spectral density vs. frequency 1s/div gain = 1000, 100nv/div gain = 1, 2v/div 09412-086 figure 39 . 0.1 hz to 10 hz rti voltage noise, g = 1, g = 1000 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 10 100 1k 10k 100k noise (pa/hz) frequenc y (hz) 09412-087 figure 40 . cu rrent noise spectral density vs. frequency
ad8229 data sheet rev. b | page 14 of 24 50pa/div 1s/div 09412-088 figure 41 . 1 hz to 10 hz current noise 0 5 10 15 20 25 30 100 1k 10k 100k 1m 10m output vo lt age (v p-p) frequenc y (hz) g = 1 v s = 15v v s = 5v 09412-089 figure 42 . large signal frequency response 5v/div 0.002%/div 750ns to 0.01% 872ns to 0.001% time ( s) 2 s/div 09412-090 figure 43 . large signal pulse response and settling time (g = 1), 10 v step, v s = 15 v 5v/div 2 s/div 640ns to 0.01% 896ns to 0.001% time ( s) 0.002%/div 09412-091 figure 44 . large signal pulse response and settling time (g = 10), 10 v step, v s = 15 v 50mv/div50mv/div 1s/div 09412-048 g = 1 25c 175c 210c 225c figure 45 . small signal respons e, g = 1, r l = 10 k , c l = 100 pf 20mv/div20mv/div 1s/div 09412-049 g = 10 25c 175c 210c 225c figure 46 . small signal response, g = 10, r l = 10 k , c l = 100 pf
data sheet ad8229 rev. b | page 15 of 24 25 c 17 5 c 21 0 c 22 5 c g = 100 2 s/div 20mv/div 09412-094 figure 47 . small signal response, g = 100, r l = 10 k , c l = 100 pf g = 1000 10 s/div 20mv/div 25 c 17 5 c 21 0 c 22 5 c 09412-095 figure 48 . small signal response, g = 1000, r l = 10 k , c l = 100 pf g = 1 1s/div 50m v/div no load c l = 100 pf c l = 147 pf 09412 - 093 figure 49 . small signal response with various capacitive loads, g = 1, r l = infinity 0 200 400 600 800 1000 1200 1400 2 4 6 8 10 12 14 16 18 20 settling time (ns) step size (v) settled to 0.001% settled to 0.01% 09412-092 figure 50 . settling time vs. step size, g = 1 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1k 10k 100k amplitude (percentage of fundamental) frequenc y (hz) no load 2k load 600 load g = 1, second harmonic v out = 10v p-p 09412-096 figure 51 . second harmonic distortion vs. frequency, g = 1 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1k 10k 100k amplitude (percentage of fundamental) frequenc y (hz) no load 2k load 600 load g = 1, third harmonic v out = 10v p-p 09412-097 figure 52 . third harmonic distortion vs. frequency, g = 1
ad8229 data sheet rev. b | page 16 of 24 0.0001 0.001 0.01 0.1 1 10 100 1k 10k 100k amplitude (percentage of fundamental) frequency(hz) no load 2k load 600 load g = 1000, second harmonic v out = 10v p-p 09412-098 figure 53 . second harmonic distortion vs. fre quency, g = 1000 0.0001 0.001 0.01 0.1 1 10 100 1k 10k 100k amplitude (percentage of fundamental) frequenc y (hz) no load 2k load 600 load g = 1000, third harmonic v out = 10v p-p 09412-099 figure 54 . third harmonic distortion vs. frequency, g = 1000 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1k 10k 100k thd (%) frequenc y (hz) gain = 1 gain = 100 v out = 10v p-p r l 2k gain = 10 gain = 1000 09412-100 figure 55 . thd vs. frequency
data sheet ad8229 rev. b | page 17 of 24 theory of operation a3 a1 a2 q2 q1 c1 c2 +in ?in +v s ?v s +v s ?v s +v s ?v s r3 5k? r4 5k? r5 5k? rg? +v s ?v s output ref node 1 node 2 i b compensat io n i b compensat io n r g v b i i +v s ?v s +v s ?v s r6 5k? rg+ r2 3k? r1 3k? 09412 - 058 figure 56 . simplified schematic architecture the ad8229 is based on the classic 3- op - amp topology. this topology has two stages: a preamplifier to provide differential amplif ication followed by a difference amplifier that removes the common - mode voltage and provides additional amplification . figure 56 shows a simplified schematic of the ad8229 . the first stage works as follows. to keep its two inputs matched, amplifier a1 must keep the collector of q1 at a constant voltage. it does this by forcing rg ? to be a precise diode drop from C in. similarly , a2 forces rg+ to be a constant diode drop from +in. therefore, a replica of the differential input voltage is pla ced across the gain setting resistor, r g . the current that flows through this resistance must also flow through the r1 and r2 resistors, creating a gained differential signal between the a2 and a1 outputs. the second stage is a g = 1 difference amplifier, composed of amplifier a3 and the r3 through r6 resistors . this stage removes the common - mode signal from the amplified differential signal. the transfer function of the ad8229 is v out = g ( v in+ ? v in? ) + v ref where: g r g k6 1 += gain selection placing a resistor across the r g terminals sets the gain of the ad8229 , which can be calculated by referring to table 5 or by using the following gain equation: 1 k 6 ? = g r g table 5 . gains achieved using 1 resistors 1% standard table value of r g (?) calculated gain 6.04 k 1.99 3 1.5 k 5.000 665 10. 02 316 19.99 121 50.59 60.4 100.34 30.1 200.34 12.1 496.9 6.04 994.4 3.01 1994.355 the ad8229 defaults to g = 1 when no gain resistor is used. the tolerance and gain drift of the r g resist or should be added to the ad8229 s specifications to determine the total gain accuracy of the system. when the gain resistor is not used, gain error and gain drift are minimal. r g p ower dissipation the ad 8229 duplicate s the differential voltage across its inputs onto the r g resistor. the r g resistor size should be chosen to handle the expected power dissipation. reference terminal the output voltage of the ad82 29 is developed with respect to the potential on the reference terminal. this is useful when the output signal must be offset to a precise midsupply level. for example, a voltage source can be tied to the ref pin to level - shift the output so that the ad8229 can drive a single - supply adc. the ref pin is protected with esd diodes and should not exceed either +v s or ?v s by more than 0.3 v.
ad8229 data sheet rev. b | page 18 of 24 for best performance, source impedance to the ref terminal should be kept well below 1 . as shown in figure 56, the reference terminal, ref, is at one end of a 5 k resistor. additional impedance at the ref terminal adds to this 5 k resistor and results in amplification of the signal connected to the positive input. the amplification from the additional r ref can be calculated as follows: 2(5 k + r ref )/(10 k + r ref ) only the positive signal path is amplified; the negative path is unaffected. this uneven amplification degrades cmrr. incorrect v correct ad8229 op1177 + ? v ref ad8229 ref 09412-059 figure 57. driving the reference pin input voltage range figure 11 through figure 16 show the allowable common-mode input voltage ranges for various output voltages and supply voltages. the 3-op-amp architecture of the ad8229 applies gain in the first stage before removing common-mode voltage with the difference amplifier stage. internal nodes between the first and second stages (node 1 and node 2 in figure 56) experience a combination of a gained signal, a common-mode signal, and a diode drop. this combined signal can be limited by the voltage supplies even when the individual input and output signals are not limited. layout to ensure optimum performance of the ad8229 at the pcb level, care must be taken in the design of the board layout. the pins of the ad8229 are arranged in a logical manner to aid in this task. 8 7 6 5 1 2 3 4 ?in r g r g +v s v out ref ?v s +in top view (not to scale) ad8229 09412-060 figure 58. pinout diagram common-mode rejection ratio over frequency poor layout can cause some of the common-mode signals to be converted to differential signals before reaching the in-amp. such conversions occur when one input path has a frequency response that is different from the other. to keep cmrr over frequency high, the input source impedance and capacitance of each path should be closely matched. additional source resistance in the input path (for example, for input protection) should be placed close to the in-amp inputs, which minimizes their interaction with parasitic capacitance from the pcb traces. parasitic capacitance at the gain setting pins can also affect cmrr over frequency. if the board design has a component at the gain setting pins (for example, a switch or jumper), the component should be chosen so that the parasitic capacitance is as small as possible. power supplies a stable dc voltage should be used to power the instrumentation amplifier. noise on the supply pins can adversely affect perfor- mance. see the psrr performance curves in figure 18 and figure 19 for more information. a 0.1 f capacitor should be placed as close as possible to each supply pin. as shown in figure 59, a 10 f tantalum capacitor can be used farther away from the part. in most cases, it can be shared by other precision integrated circuits. ad8229 + v s +in ?in load r g ref 0.1f 10f 0.1f 10f ?v s v out 09412-061 figure 59. supply decoupling, ref, and output referred to local ground reference pin the output voltage of the ad8229 is developed with respect to the potential on the reference terminal. care should be taken to tie ref to the appropriate local ground.
data sheet ad8229 rev. b | page 19 of 24 input bias current r eturn path the input bias current of the ad8229 must have a return path to ground. when using a floating source without a current return path , such as a thermocouple, a current return path should be created, as shown in figure 60 . thermocouple +v s ref ?v s ad8229 capacitively coupled +v s ref c c ?v s ad8229 transformer +v s ref ?v s ad8229 incorrect capacitively coupled +v s ref c r r c ?v s ad8229 1 f high-pass = 2rc thermocouple +v s ref ?v s 10m? ad8229 transformer +v s ref ?v s ad8229 correct 09412-062 figure 60 . creating an input bias current return path input protection the inputs to the ad8229 should be kept within the ratings stated in the absolute maximum ratings section. if this cannot be done, protection circuitry can be added in front of the ad8229 to limit the current into the inputs to a maximum current , i max . input voltages b eyond the rails if voltages be yond the rails are expected, use an external resistor in series with each input to limit current during overload conditions. the limiting resistor at the input can be computed from max supply in protect i vv r | | ? noise - sensitive applications may require a lower p rotection resistance. low leakage diode clamps, such as the bav199, can be used at the inputs to shunt curr ent away from the ad8229 inputs and therefore allow smaller protection resistor values. to ensure curre nt flows primarily through the e xternal protection diodes, place a small value resistor, such as a 33 , between the diodes and the ad8229 . simple method low noise method +v s ad8229 r protect r protect ?v s i v in+ + ? v in? + ? 09412-066 +v s +v s ad8229 r protect 33? 33? r protect ?v s ?v s i v in+ + ? v in? + ? +v s ?v s figure 61 . protection for voltages beyond the rails large differential input voltage at high gain if large differential voltages at high gain are expected, use an external resistor in series with each input to limit current during overload conditions. the limiting resistor at each input can be computed from ? ? ? ? ? ? ? ? ? ? g max diff protect r i vv r 1|| 2 1 noise - sensitive applications may require a lower protection resistance. low leakage diode clamps, such as the bav199, can be used across the inputs to shunt current away from the ad8229 inputs and therefore allow smaller protection resistor values. 09412-067 ad8229 r protect r protect i v diff + ? ad8229 r protect r protect i v diff + ? simple method low noise method figure 62 . protection for large differential voltages i max the maximum current into the ad8229 inputs, i max , depends on both time and temper ature. at room temperature, the part can withstand a cu rrent of 10 ma for at least a day . this time is cumulative over the lif e of the part. at 210c, limit current to 2 m a for the same period. the part can withstand 5 ma at 210c for an hour, cumulat ive o ver the life of the part. radio frequency inte rference (rfi) rf rectification is often a problem when amplifiers are used in applications that have strong rf signals. the disturbance can appear as a small dc offset voltage. high frequency signals can be fi ltered with a low - pass rc network placed at the input of the instrumentation amplifier, as shown in figure 63 . the filter limits the input signal bandwidth, according to the following relationship: )2(2 1 c d diff ccr uency filterfreq + = c cm rc uency filterfreq 2 1 = where c d 10 c c .
ad8229 data sheet rev. b | page 20 of 24 r r ad8229 + v s +in ?in 0.1f 10f 10f 0.1f ref v out ?v s r g c d 10nf c c 1nf c c 1nf 4.02k ? 4.02k ? 09412-063 figure 63. rfi suppression c d affects the difference signal, and c c affects the common-mode signal. values of r and c c should be chosen to minimize rfi. a mismatch between r c c at the positive input and r c c at the negative input degrades the cmrr of the ad8229 . by using a value of c d one magnitude larger than c c , the effect of the mismatch is reduced, and performance is improved. resistors add noise; therefore, the resistor and capacitor values chosen depend on the desired tradeoff between noise, input impedance at high frequencies, and rfi immunity. the resistors used for the rfi filter can be the same as those used for input protection. calculating the noise of the input stage the total noise of the amplifier front end depends on much more than the 1 nv/hz headline specification of this data sheet. there are three main contributors: the source resistance, the voltage noise of the instrumentation amplifier, and the current noise of the instrumentation amplifier. in the following calculations, noise is referred to the input (rti). in other words, everything is calculated as if it appeared at the amplifier input. to calculate the noise referred to the amplifier output (rto), simply multiple the rti noise by the gain of the instrumentation amplifier. r2 r g r1 sensor ad8229 09412-064 figure 64. ad8229 with source resistance from sensor and protection resistors source resistance noise any sensor connected to the ad8229 has some output resistance. there may also be resistance placed in series with inputs for protection from either overvoltage or radio frequency interference. this combined resistance is labeled r1 and r2 in figure 64. any resistor, no matter how well made, has a minimum level of noise. this noise is proportional to the square root of the resistor value. at room temperature, the value is approximately equal to 4 nv/hz (resistor value in k). for example, assuming that the combined sensor and protection resistance on the positive input is 4 k, and on the negative input is 1 k, the total noise from the input resistance is 2 2 )14()44( ??? = 1664 ? = 8.9 nv/ hz voltage noise of the instrumentation amplifier the voltage noise of the instrumentation amplifier is calculated using three parameters: the part input noise, output noise, and the r g resistor noise. it is calculated as follows: total voltage noi se = 2 2 2 ) () ()/ ( resistorrofnoise noiseinputgnoise output g ? ? for example, for a gain of 100, the gain resistor is 60.4 . therefore, the voltage noise of the in-amp is 2 22 )0604.04(1)100/45( ??? = 1.5 nv/hz current noise of the in strumentation amplifier current noise is calculated by multiplying the source resistance by the current noise. for example, if the r1 source resistance in figure 64 is 4 k, and the r2 source resistance is 1 k , the total effect from the current noise is calculated as follows: ))5.11()5.14(( 2 2 ??? = 6.2 nv/hz total noise density calculation to determine the total noise of the in-amp, referred to input, combine the source resistance noise, voltage noise, and current noise contribution by the sum of squares method. for example, if the r1 source resistance in figure 64 is 4 k, the r2 source resistance is 1 k , and the gain of the in-amps is 100, the total noise, referred to input, is )2.65.19.8 2 22 ?? = 11.0 nv/hz
data sheet ad8229 rev. b | page 21 of 24 outline dimensions 07-08-2010-b 0.054 nom 0.032 nom 0.130 nom 8 5 1 4 0.320 0.310 0.300 0.298 0.290 0.282 0.528 0.520 0.512 0.305 0.300 0.295 0.125 0.110 0.095 0.310 0.300 0.290 0.105 0.095 0.085 0.020 0.018 0.016 0.105 0.100 0.095 0.045 0.035 0.025 0.011 0.010 0.009 0.011 0.010 0.009 index mark seating plane 0.175 nom figure 65 . 8 - lead side - brazed ceramic dual in - lin e package [sbdip] (d-8- 1) dimensions s hown in inches controlling dimensions are i n millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference o nl y and are not appropriate for use in des ign. compliant to jedec standards ms-012-aa 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 8 5 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 66 . 8 - lead standard small outline package [soic_n] narrow body (r- 8) dimensions shown in millimeters and (inches) ordering guide model 1 temperature range package des cription package option ad8229hdz ?40c to +210c 8 - lead side - brazed ceramic dual in - line package [sbdip] d - 8 - 1 AD8229HRZ ?40c to +175c 8 - lead standard small outline package [ soic_n ] r - 8 ad822 9 hrz - r7 ?40c to +175c 8- lead standard small outline package [soic_n] r-8 1 z = rohs compliant part.
ad8229 data sheet rev . b | page 22 of 24 notes
data sheet ad8229 rev. b | page 23 of 24 notes
ad8229 data sheet rev . b | page 24 of 24 notes ? 2011 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09412 -0- 2/12(b )

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